परमाणु ऊर्जा विभाग, भारत सरकार का एक स्वयंशासित संस्थान
An Autonomous Institute under DAE, Government of India
An Autonomous Institute under DAE, Government of India
Manoj Mishra
Reader - F
Computer Science
manoj.mishra@niser.ac.in
Education
11/2016 - 10/2018 School of Electrical Engineering - Systems,
Tel-Aviv University, Israel
Postdoctoral Fellow
Advisors: Benny Applebaum, Ofer Shayevitz
01/2011 - 07/2016 Indian Institute of Technology Bombay, Mumbai, India
Ph.D. in Electrical Engineering
Advisors: Bikash Kumar Dey, Vinod M. Prabhakaran
08/2008 - 12/2010 University of Notre Dame, South Bend, Indiana, USA
M.S.E in Electrical Engineering
Advisors: Daniel J. Costello, Jr., Thomas E. Fuja
Specialization: FPGA-based decoder for LDPC Convolutional
Codes
09/2000 - 04/2002 University of Michigan, Ann Arbor, Michigan, USA
M.S. in Computer Science and Engineering
Specialization: Computer Architecture, Testing, Algorithms
07/1994 - 05/1998 Indian Institute of Technology Kharagpur, West Bengal, India
B.Tech.(Hons.) in Electronics and Electrical Communication
Engineering
Teaching
- CS452 - Algorithmic Coding Theory (Even Semester, 2018-19)
- CS654/454 - Convex Optimization Theory (Odd Semester, 2019-20)
- CS664 - Secure Multiparty Computation (Even Semester, 2019-20)
Awards
- Postdoctoral Fellowship from Tel-Aviv University.
- Award for “Excellence in Thesis Work for 2015 – 2017” (Best Thesis Award), awarded by IIT Bombay for “outstanding research contributions”.
- University of Notre Dame, Dept. of Electrical Engg.'s Research Assistantship.
- University of Michigan’s Rackham School Fellowship to pursue Graduate Studies in Computer Science and Engg. – Hardware
Publications
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A.K. Yadav, M. Mamindlapally, A.J. Budkuley, M. Mishra, "Commitment over Compound Binary Symmetric Channels", National Conference on Communications (NCC), 2021
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M. Mamindlapally, A.K. Yadav, M. Mishra, A.J. Budkuley, "Commitment Capacity under Cost Constraints", IEEE International Symposium on Information Theory (ISIT), 2021
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V. Narayanan, M. Mishra, V. M. Prabhakaran, "Private Two-Terminal Hypothesis Testing", IEEE International Symposium on Information Theory (ISIT), 2020
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B. Applebaum, T. Holenstein, M. Mishra, O. Shayevitz, “The Communication Complexity of Private Simultaneous Messages, Revisited”, Journal of Cryptology, vol. 33, pp. 917-953, 2020
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B. Applebaum, T. Holenstein, M. Mishra, O. Shayevitz, “The Communication Complexity of Private Simultaneous Messages, Revisited”, International Conference on the Theory and Applications of Cryptographic Techniques (EUROCRYPT), 2018
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M. Mishra, B. K. Dey, V. M. Prabhakaran, S. Diggavi, “Wiretapped Oblivious Transfer”, IEEE Transactions on Information Theory, vol. 63, iss. 4, pp. 2560 - 2595, 2017
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M. Mishra, T. Sharma, B. K. Dey, V. M. Prabhakaran, “Private Data Transfer over a Broadcast Channel”, IEEE International Symposium on Information Theory (ISIT), 2015
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M. Mishra, B. K. Dey, V. M. Prabhakaran, S. Diggavi, “On the oblivious transfer capacity of the degraded 1-of-2wiretapped binary erasure channel”, IEEE International Symposium on Information Theory (ISIT), 2015
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M. Mishra, B. K. Dey, V. M. Prabhakaran, S. Diggavi, “On the oblivious transfer capacity region of the binary erasure broadcast channel”, IEEE Information Theory Workshop, Hobart (ITW), 2014
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D. Data, B. K. Dey, M. Mishra, V. M. Prabhakaran, “How to Securely Compute the Modulo-Two Sum of Binary Sources”, IEEE Information Theory Workshop, Hobart (ITW), 2014
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M. Mishra, B. K. Dey, V. M. Prabhakaran, S. Diggavi, “The oblivious transfer capacity of the wiretapped binary erasure channel”, IEEE International Symposium on Information Theory (ISIT), 2014
Research
- Unconditionally Secure Two-Party and Multi-Party Computations
- Information Theory
Other Links
Professional Experience
12/2004 - 04/2008 Ikanos Communications (India) Pvt. Ltd., Bangalore, India
Senior Member Technical Staff
Architecting, designing and lab-testing subsystems for x-DSL ASICs
12/2003 - 12/2004 Raza Microelectronics (India), Bangalore, India
Member Technical Staff
Design & verification of subsystems for SONET/SDH & Ethernet
ASICs
10/2002 - 12/2003 Broadcom (India), Bangalore, India
Member Technical Staff
Verification of subsystems for Ethernet LAN ASICs
06/1998 - 07/2000 S3 (India), Bangalore, India
Member Technical Staff
Full-chip synthesis and timing for Ethernet LAN ASICs
Phone No.
-2494708
Room No.
